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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
Table 4. Signal De?nitions for Quad SPI-3 to SPI-4 Link Bridge Solution I/O (Continued)
Signal Name
ATDCLKP
ATDCLKN
ATSTAT[1:0]P
ATSTAT[1:0]N
ATSCLKP
ATSCLKN
TSTAT[1:0]A
TSCLKA
Direction
Output
Input
Input
Input
Input
Description
Differential TXA clock signal
LVDS Status Input
LVDS Status Input clock
LVTTL Status Input
LVTTL Status Clock Input
ORSPI4 Embedded Core Control, Global I/O and FPGA Con?guration I/O 3
1. The signals listed here are required for a single SPI-3 interface. The signals should be replicated for each additional SPI-3 Interface instan-
tiation.
2. The signals listed here are required for the SPI-4 interface A (signal names are prefaced with the letter “A”). Please refer to the ORSPI4
Data Sheet for additional information on con?guring the SPI-4 interface for speci?c applications.
3. Please refer to the ORCA Series 4 FPGA Data Sheet and the ORSPI4 Data Sheet for information on the various con?guration options.
Table 5. Signal De?nitions for Quad SPI-3 to SPI-4 Link Bridge Solution - FPGA/Embedded ASB Interface
(Internal to ORSPI4 Device)
Signal Name
Transmit Interface Signals
SPIA_RX32_CLKx
RX_D[31:0]
RX_D[32]
RX_D[33]
RX_D[37:34]
RX_D[38]
RX_D[39]
RX_FIFO_EMPTY
RX_A[2:0]
RX_RE
Transmit Status Signals
RX_PSS_CLK
RX_EXT_STATUS_EN
RX_PORT_STATUS[1:0]
RX_FPGA_PORTID[7:0]
RX_PSS_WE
Receive Status Signals
ATREFCLK
TX_SPI_CLK
TX_PORT_ID[7:0]
TX_BKP
TX_STAT[1:0]
Receive Interface Signals
SPIA_TX32_CLKx
TX_D[31:0]
FPGA Direction
Output
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Input
Output
Input
Input
Input
Output
Output
Description
Read Clock to DPRAM Bank 0
Read Data from DPRAM Bank 0
SOP Indicator from DPRAM Bank 0
EOP Indicator from DPRAM Bank 0
Byte Valid Indicator from DPRAM Bank 0
Error Indication for Read Data
Port ID Indicator (RSX in SPI-3)
FIFO Empty Flag from DPRAM Bank 0
Read Address to DRPAM Bank 0
Read Enable to DPRAM Bank 0
Write Clock to PSS Memory
Indicates Valid Status
2-bit status for Port speci?ed by TX_Port_ID
Address of Port for which Status is provided
Write Enable to PSS Memory
SPI-4 Transmit Reference Clock
SPI-3 Transmit Clock
Address of Port for which Status is provided
SPI-4 Backpressure to FPGA
Status of Port speci?ed by TX_PORT_ID
Write Clock to DPRAM Bank 0
Write Data to DPRAM Bank 0
11
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